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MT91610
Programmable Ringing SLIC Preliminary Information
Features
* * * * * * * * * * * * * * * Transformerless 2W to 4W conversion Controls battery feed to line Programmable line impedance Programmable network balance impedance Off-hook and dial pulse detection Protects against GND short circuit Programmable gain Programmable constant current mode with constant voltage fold over Transformerless balanced ringing with automatic ring trip circuit. No mechanical relay Supports low voltage ringing Line polarity reversal On-hook transmission Power down and wake up capability Meter pulse injection Ground Key detection
DS5181 ISSUE 6 July 2001
Package Information MT91610AQ 36 Pin QSOP Package
-40C to +85C
Description
The Zarlink MT91610, with an external bipolar driver (Figure 4), provides an interface between a switching system and a subscriber loop. The functions provided by the MT91610 include battery feed, programmable constant current with constant voltage fold over for long loops, 2W to 4W conversion, off-hook and dial pulse detection, direct balance ringing with built in ring tripping, unbalance detection, user definable line and network balance impedance's and gain, and power down and wake up. The device is fabricated as a CMOS circuit in a 36 pin QSOP package.
Applications
Line interface for: * PABX * Intercoms * Key Telephone Systems * Control Systems
PD
RV RC
GTX1 ESE
ESI
GTX0
TD
Tip Drive Controller
Ringing Controller
Audio Gain & Network Balance Circuit
VX VR
TF TIP RING RF
Z3 Line Sense 2 W to 4 W Conversion & Line Impedance Z2 Z1 CP5 Line Reverse Driver LR
Over-Current Protection Circuit
RD
Ring Drive Controller
Loop Supervision
VDD
VREF
DCRI
GND
VEE
CP2
CP3
Figure 1 - Functional Block Diagram
SHK UD
CP4 CP6 CP7
VBAT
CP1
1
MT91610
VDD TD TF NC TIP VREF LR RING RF NC RD CP1 CP2 CP3 CP4 ESE PD DCRI 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 VEE RV CP7 SHK VBAT UD RC CP6 VR GTX1 ESI VX GTX0 Z3 Z2 CP5 Z1 AGND
Preliminary Information
Figure 2 - Pin Connections
Pin Description
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Name VDD TD TF NC Tip VREF LR Ring RF NC RD CP1 CP2 CP3 CP4 ESE PD DCRI AGND Positive supply rail, +5V. Tip Drive (Output). Controls the Tip transistor. Connects 330nF cap to GND. Tip Feed (Output). Connects to the Tip transistor and to TIP via the Tip feed resistor. No Connection. Left open. Tip. Connects to the TIP lead of the telephone line. Reference Voltage (Input). Used to set the subscribers loop constant current. A 0.1uF cap should be connected between this pin and GND for noise decoupling. Line Reverse (Input). This pin should be set to 0V for NORMAL polarity. Setting the pin to +5V reverses the polarity of Tip and Ring. Ring. Connects to the RING lead of the telephone line. Ring Feed (Output). Connects to the RING lead via the Ring feed resistor. No Connection. Left open. Ring Drive (Output). Controls the Ring transistor. Connects 330nF cap to GND. CP1. A 100nF capacitor should be connected between this pin and pin 13. CP2. A 220nF capacitor for loop stability is connected between this pin and pin 14. CP3. A 220nF capacitor for loop stability is connected between this pin and pin 13. CP4. A 100nF cap should be connected between this pin and GND. External Signal Enable (Input). A logic '1' enables the MPI (Meter Pulse Input) to Tip / Ring. This pin should be set to logic '0' when not used. Power Down (Input). A logic '1' power down the device. This pin should be set to logic '0' for normal operation. DC voltage for Ringing Input (Input) The positive voltage supply for balance ringing. The input DC voltage range is from 0V to +72V. Analog Ground. 4 Wire Ground, normally connected to system ground. Description
2
Preliminary Information
Pin Description (continued)
Pin # 20 21 22 23 24 25 26 27 28 29 30 Name Z1 CP5 Z2 Z3 GTX0 VX ESI GTX1 VR CP6 RC Description
MT91610
Line Impedance Node 1. A resistor of scaled value "k" is connected between Z1 and Z2. This connection can not be left open circuit. Line Impedance AC couple. A 330 nF cap must be connected between this pin and Z1 (pin 20). Line Impedance Node 2. This is the common connection node between Z1 and Z3. Line Impedance Node 3. A resistive or complex network of scaled value "k" is connected between Z3 and Z2. This connection can not be left open circuit. Gain Node 0. This is the common node between Z3 and VX where resistors are connected to set the 2W to 4W gain. Transmit Audio. 4W analog signal from the SLIC. External Signal Input. 12 / 16 KHz signal input. Gain Node 1. The common node between VR and the audio input from the CODEC or switching network where resistors are fitted to set the 4W to 2W gain. Receive Audio. 4W analog signal to the SLIC. Ringing Cap. A 0.47uF cap should be connected between this pin and GND to filter out the ringing signal. Ringing Control. An active high (+5V) on this pin will set up the DC feed and gain of the SLIC to apply 20 Hz ringing. When low (0V) set the SLIC in normal constant current mode of operation. UnBalance Detect. Logic high (+5V) indicates an offset current between Tip and Ring. VBAT. The negative battery supply, typically at -48V. Switch Hook. This pin indicates the line state of the subscribers telephone. The output can also be used for dial pulse monitoring. Logic high (+5V) indicates off hook condition. Deglitching Cap. A 33nF should be connected between this pin and GND. Ringing Voltage. 20 Hz sinusoidal or square wave AC in for balance ringing. Negative supply rail, -5V. 4 wire signal, which is the output from the SLIC to the analog switch or voice CODEC. components
31 32 33 34 35 36
UD VBAT SHK CP7 RV VEE
Functional Description
Refer to Figure designation. 4 for MT91610
Gain Control
It is possible to set the Transmit and Receive gains by the selection of the appropriate external components. The gains can be calculated by the following formulae: 2W to 4W gain Gain 2 - 4 = 20 Log [ R8 / R7] 4W to 2W gain Gain 4 - 2 = 20 Log [0.891 * [R10 / R9)]
The MT91610, with external bipolar transistors, functions as an Analog Line SLIC for use in a 4 Wire switched system. The SLIC performs all of the BORSH functions while interfacing to a CODEC or switching system. 2 Wire to 4 Wire Conversion The SLIC performs 2 wire to 4 wire conversion by taking the 4 wire signal from an analog switch or voice CODEC, and converting it to a 2 wire differential signal at Tip and Ring. The 2 wire signal applied to tip and ring by the phone is converted to a
3
MT91610
Impedance Programming
The MT91610 allows the designer to set the device's impedance across TIP and RING, (ZTR), and network balance impedance, (ZNB), separately with external low cost components. The impedance (ZTR) is set by R4, R5, while the network balance, (ZNB), is set by R6, R8, (see Figure 4.) The network balance impedance should calculated once the 2W - 4W gain has been set. be
Preliminary Information
Loop Supervision
The Loop Supervision circuit monitors the state of the phone line and when the phone goes "Off Hook" the SHK pin goes high to indicate this state. This pin reverts to a low state when the phone goes back "On Hook" or if the loop resistance is too high (>2.3K) When loop disconnect dialling is being used, SHK pulses to logic 0 indicate the digits being dialled. This output should be debounced.
Constant Current Control & Voltage Fold Over Mode
The SLIC employs a feedback circuit to supply a constant feed current to the line. This design is accomplished by sensing the sum of the voltages across the feed resistors, Ra and Rb, and comparing it to the input reference voltage, Vref, that determines the constant current feed current. By using a resistive divider network, (Figure 3), it is possible to generate the required voltage to set the loop current, ILOOP. This voltage can be calculated using the following formula: ILOOP = [VDD * G] * 3 (Ra +Rb) where, G = R2 / (R1 + R2) I LOOP is in Ampere. R1= 200K Ra = Rb = 100 R2 = 72.73 K R2 = 100 K R2 = 133.33 K
Line Impedance
For optimum performance, the characteristic impedance of the line, (Zo), and the device's impedance across TIP and RING, (ZTR), should match. Therefore: Zo = ZTR The relationship between Zo and the components that set ZTR is given by the formula: Zo / ( Ra+Rb) = kZo / R4 where kZo = R5 Ra = Rb The value of k can be set by the designer to be any value between 500 and 2000. R4 and R5 should be greater than 100k.
Network Balance Impedance
The network balance impedance, (ZNB), will set the transhybrid loss performance for the circuit. The transhybrid loss of the circuit depends on both the 4 2 Wire gain and the 2 - 4 Wire gain. The method of setting the values for R6 (or Z6... it can be a complex impedance) is given as below: R6 = R7 * (R9 / R10) * 2.2446689 * ( ZNB / ZNB + Zo) Please note that in the case of Zo not equal to ZNB (the THL compromized case) R6 is a complex impedance. In the general case of Zo matched to ZNB (the THL optimised case), R6 is just a single resistor.
From Figure 3 with For ILOOP = 20mA, For ILOOP = 25mA, For ILOOP = 30mA,
R2 **k
6 R1 200K
VREF
C2 0.47uF
MT91610
+5V ** See Figure 6
Figure 3 - Loop Setting
4
Preliminary Information
For convenience, a graph which plots the value of R2 (K) versus the approximated loop current is shown in Figure 6. This graph implies the SLIC is operating in constant current mode. As +5V is used as the reference voltage to generate the loop current, any noise on the +5V rail will deteriorate the PSR (Power Supply Rejection) parameter of the SLIC. It is therefore important to decouple +5V to GND. A 0.1uF cap at Vref pin (pin6) is recommended. The MT91610 operating current mode is recommended to be between 20mA and 30mA. The device will automatically switch to voltage fold over mode should an unexpected long loop situation occur for a given programmed loop current. The lowest operational current should be 16mA with VBAT set at -48V. A typical Operating Current versus Loop Resistance with VBAT at -48V is shown in Figure 7. The actually loop current should settle to within +/- 2 mA of the targeted value.
MT91610
Powering Up / Down Sequence
AGND is always connected Powering Up: +5V, -5V, VBAT PD to +5V for 100ms; PD to 0V Powering Down: VBAT, -5V, +5V
Balanced Ringing & Automatic Ring Tripping
Balanced Ringing is applied to the line by setting RC (pin 30) to +5V and connecting the ringing signal (20Hz) to RV (pin 35) as shown in Figure 4. A 1.2Vrms input will give approximately 60Vrms output across Tip and Ring, sufficient for short loop SLIC applications. The SLIC is capable of detecting an Off Hook condition during ringing by filtering out the large A.C. component. A 0.47uF cap should be connected to pin CP6 (pin 29) to form such filter. This filter allows a true Off Hook condition to be monitored at SHK (pin 33). When an Off Hook condition is detected by the SLIC, it will remove the 20Hz AC ringing voltage and revert to constant current mode. The local controller will, however, still need to deselect RC (set it to 0V). The MT91610 supports short burst of ringing cadence. A deglitching input (CP7) is provided to ensure that the SHK pin is glitch free during the assertion and de-assertion of RC. A 33nF cap should be connected from this pin to GND. A positive voltage source is required to be connected to the DCRI pin (Figure 5) for normal Ringing operation. The SLIC can perform ringing even with the DCRI input connected to 0V, however, it does require the VBAT to be lower than -48V (ie at -53V or lower) and the 20Hz AC input should be a 2Vrms square wave. The MT91610 can also be used in applications requiring unbalanced ringing using an external relay. Reference MSAN-180 for details of this and equations related to ringing.
UD & Line Drivers Overcurrent Protection
The Line Drivers control the external Battery Feed circuit which provide power to the line and allows bidirectional audio transmission. The loop supervision circuitry provides bias to the line drivers to feed a constant current. Overcurrent protection is done by the following steps: (A) External bipolar transistors to limit the current of the NPN drivers to 50mA (Figure 5, Q14, Q15, R9, R19). (B) The local controller should monitor the Unbalance Detection output (UD) for any extended period of assertion (>5 seconds). In such case the controller should power down the device by asserting the PD pin, and poll the device every 5 seconds. The UD output can be used to support GND START LOOP in a PaBX operation. Reference MSAN-180 for details. Please note that this UD output should be disregarded and masked out if RC pin is active (ie set to +5V).
Line Reversal
The MT91610 can deliver Line Reversal, which is required in operation such as ANI, by simply setting LR (pin 7) to +5V. The device transmission parameters will cease during the reversal. The LR (pin 7) should be set to 0V for all normal loop operations.
5
MT91610
Power Down And Wake Up
The MT91610 should normally be powered down to conserve energy by setting the PD pin to +5V. The SHK pin will be asserted if the equipment side (2 wire) goes off hook. The local controller should then restore power to the SLIC for normal operations by setting the PD pin to 0V. Please note that there will be a short break (about 80ms) in the assertion time of SHK due to the time required for the loop to power up and loop current to flow. The local controller should be able to mask out this time.
Preliminary Information
Zo = 600, ZNB= 600, Ra=Rb= 100 Gain 2 - 4 = -6dB, Gain 4 - 2 = -1 dB Step 1: Gain Setting (R7, R8, R9, R10) Gain 2 - 4 = 20 Log [ R8 / R7] -6 dB = 20 Log [R8 / R7] choose R7 = 300k, R8 = 150k. Gain 4 - 2 = 20 Log [0.891 * [R10 / R9)] -1 dB = 20 Log [0.891 * [R10/ R9)] choose R9 = 200k, R10 = 200k. Step 2: Impedance Matching (R4, R5)
Meter Pulse Injection
The MT91610 provides a gain path input (ESI) for meter pulse injection and an independent control logic input (ESE) for turning the meter pulse signal on and off. Gain (meter pulse) = 20 Log [0.891 * (R10 / R11)] with configuration targeting Zo = 220 + (820 // 115nF) Zo / ( Ra+Rb) = kZo / R4, where kZo = R5 Zo / ( Ra+Rb) = kZo / R4 600/(100+100) = k*(600)/R4 let k=500 R4= 100k kZo = R5 500*600=R5 R5= 300k Step 3: Network Balance Impedance (R6) Optimised Case Zo = ZNB R6 = R7 * (R9 / R10) * 2.2446689 * ( ZNB / ZNB + Zo) R6 = 300k * (1) * 1.1223344 R6= 336.7k Step 4: The Loop Current (R2) Calculating Component Values There are five parameters a designer should know before starting the component calculations. These five parameters are: 1) 2) 3) 4) 5) characteristic impedance of the line Zo network balance impedance ZNB value of the feed resistors (Ra and Rb) 2W to 4W transmit gain 4W to 2W receive gain In order to remain in constant current mode during normal operation, it is necessary that the following equation holds: {| I * Zt |} V < { | VBAT | - 6*VREF - 2} V where, I = Desirable Loop Current Zt = Ra + Rb + maximum DC loop resistance VBAT = Battery voltage VREF= DC voltage at VREF pin
Component Selection
Feed Resistors The selection of feed resistors, Ra and Rb, can significantly affect the performance of the MT91610. The value of 100 is used for both Ra and Rb. The resistors should have a tolerance of 1% (0.1% matched) and a power rating of 0.5 Watt.
The following example will outline a step by step procedure for calculating component values. Given:
6
Preliminary Information
Given the parameters as follows: Ra = Rb = 100 Expected maximum loop impedance = 1.6k (including Ra and Rb) Desirable Loop Current = 20mA 6*VREF=8V Then | VBAT | (min) = 1600 * 0.020 +10 = 42V Assume that the VBAT of 42V is available, then read the value of R2 from Figure 6, which is 72k. Step 5: Calculation Of Non-Clipping Sinusoidal Ringing Voltage At Tip Ring (VTR) Assume the peak Ringing Current is less than 50mA, the ringing voltage (20Hz) at Tip and Ring is given as: VTR (rms) = 0.707 * {| VBAT | + VDCRI - (15.6 * VREF)} VDCRI= Positive DC voltage at DCRI pin VBAT = Negative Battery voltage VREF= Positive DC voltage at VREF pin AC voltage at the RV input pin is therefore RV (rms)~= VTR (rms) / 50
MT91610
7
MT91610
Preliminary Information
+5V C5 C4
-5V
1 VDD VEE 36 TD C14 TF NO CONNECT F1 TIP PR1 RING F2 TIP/RING DRIVER
+5V PD RF RING RD -5V TD TCI 19 TIP TIP 18 TF TF 17 RC RC 16 VBAT VBAT 15 TF_BR 14 VBAT 8 VBAT AGND 13 9 RF_BR DCRI 12 DCRI VBAT 10 NC VBAT 11 1 VDD 2 PD 3 RF 4 RING 5 RCI 6 VEE 7 NC
2 TD RV 35 Z1 20 C10 CP5 21 R4
**C6 RING VOLTAGE
3 TF 4 NC 5 TIP
**R3
TIP
RING
8 RING
Z2 22 R5
RF
9 RF Z3 23 GTX0 24 R8 R7 R6
BR
BR
VX 25 ESI 26
R11 R12
VX_OUT **C8 ESI
C13
12 CP1 13 CP2
GTX1 27 R10 VR 28 UD 31
R9
VR_IN
D1**
C1 14 CP3 C9 UNBALANCE DETECTION
C7 SHK R13 C12 15 CP4 VBAT 32 VBAT VBAT_IN SHK
DCRI_IN
DCRI
18 DCRI
SHK 33
SWITCH HOOK
34 CP7 C11
CP6 29 C3 ESE 16 ESE ESE
RD C15
11 RD PD 17 LR 7
PD
POWER DOWN LINE REVERSE
NO CONNECT +5V R1 R2 C2 10 NC 6 VREF 19 AGND RC 30 RC RING CONTROL
= Ground (Earth)
** Optional
Figure 4 - Typical Application with a Resistive 600 ohm Line Impedance
8
Preliminary Information
MT91610
Component List* for a Typical Application with a Resistive 600 Line Impendance - Refer to
Figure 4 for component designation and recommended configuration
Resistor Values R1 R3 R5 R7 R9 R11 R13 200k 200k 300k 300k 200k 200k 51k Capacitor Values C1 C3 C5 C7 C9 C11 C13 C15 220nF, 5% 470nF, 5% 100nF, 5% 100nF, 5% 10nF, 5% 33nF, 5% 100nF, 5% 330nF, 5% C2 C4 C6 C8 C10 C12 C14 470nF, 5% 100nF, 5% 4.7uF, 5% 100nF, 5% 330nF, 5% 100nF, 5% 330nF, 5% R2 R4 R6 R8 R10 R12 100k (see Figure 6) 100k 336k7 150k 200k 10k
Note: All resistors are 1/8 W, 1% unless otherwise indicated. *Assumes Z o = Z NB = 600, Gain 2 - 4 = -6dB, Gain 4 - 2 = -1dB.
D1 PR1
= =
1N5819 Schottky Diode (Optional) This device must always be fitted to ensure damages does not occur from inductive loads. For simple applications PR1 can be replaced by a single TVS, such as 1.5KE220C, across tip and ring. For applications requiring lightning and mains cross protection further circuitry will be required and the following protection devices are suggested: P2353AA, P2353AB (Teccor), THBT20011, THBT20012, THBT200S (SGS-Thomson), TISP72290, TISP7360F3D (T.I.) Raychem TR600-150 or equivalent Teccor F1250T Slow-Blow Fuse
BR F1, F2
= =
Protection Components
Figure 4 shows three possible combinations of protection. Depending on the application, the user can select whether to use a resettable or non-resettable protection scheme. Slow-Blow Fuse (F1, F2) in place short out in place
Method 1 2 3
Varistor (PR1) in place in place in place
Breaker (BR) short out in place in place
9
MT91610
Preliminary Information
R3
R8 D6 Q6
R1 Q7 D1 R4 RCI PIN 13 AGND PIN 1 VDD R21 PIN 2 PD R22 Vee R23 R26 R2 Q3 R6 Q14 Vbat PIN 5 AGND R7 D2 R5 R31 D7 C1
RF_BR PIN 9 RF PIN 3 Ra
RING PIN 4 Q5 Vbat R9
Q8
R25 Q13 Q4 R24 PIN 6 Vee VEE D5 Q1 Q2 R27
DCRI PIN 12 R10
R20 R13 R18 Q16 Q10 R11 D8 Q9 D3 R14 TCI PIN 19 R17 D4 R28 R12 R16 Q15 Vee Vbat R32 R15 D9 Q12 Q11 R19 Vbat VBAT_IN PIN 8, 11, 15 TIP PIN 18 Rb C2 PIN 14 TF_BR PIN 17 TF R30 AGND R29 RC PIN 16
Figure 5 - Line Driver Stage
10
Preliminary Information
Component List for the TIP/RING Line Driver configuration
MT91610
Refer to Figure 5 for component designation and recommended
Resistor Values Ra R1 R3 R5 R7 R9 R11 R13 R15 R17 R19 R21 R23 R25 R27 R29 R31 100 %1, 0.1% matched, 0.5W 2k5 2k5 470 300 11 2k5 2k5 470 300 11 30k 20k 3k 30k 20k 1k Rb R2 R4 R6 R8 R10 R12 R14 R16 R18 R20 R22 R24 R26 R28 R30 R32 Capacitor Values C1 10nF, 5% C2 Diodes and Transistors D1-D5 Q1 Q3 Q5 Q7 Q9 Q11 Q13 Q15 BAS16 or equivalent MMBTA92 or equivalent MMBTA92 or equivalent PZTA42 or equivalent MMBTA42 or equivalent MMBTA42 or equivalent PZTA42 or equivalent MMBTA92 or equivalent MMBTA42 or equivalent D6-D9 Q2 Q4 Q6 Q8 Q10 Q12 Q14 Q16 BAW101 or equivalent MMBTA92 or equivalent MMBTA42 or equivalent PZTA92 or equivalent MMBTA92 or equivalent PZTA92 or equivalent MMBTA92 or equivalent MMBTA42 or equivalent MMBTA42 or equivalent 10nF, 5% 100 %1, 0.1% matched, 0.5W 3k6 470 2k5 11 30k 3k6 470 2k5 11 25k, 1/4W 20k 20k 30k 5k1 30k 1k
Note: All resistors are 1/8 W, 1% unless otherwise indicated.
11
MT91610
Preliminary Information
R2 (Kohm) vs Loop Current (mA)
145
140
135
130
125 120
115
110
105
R2 (Kohm)
100
95
90
85
80 75
70
65
60
55 50 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Loop Current (mA)
Figure 6 - Approximated R2 (Kohm) Versus Programmed Loop Current (mA) for constant current mode applications.
12
Preliminary Information
MT91610
Loop Current (mA) versus Loop Resistance (Ohm)
31 30 29 28
27 26 25
24 23
22
21
20 19
18 17
16 15
14
13 12
11
10 9
8 0 200 400 600 800 1000 1200 1400 1600 1800 2000 2200 2400 2600 2800 3000 3200 3400 3600 3800 4000
Loop Resistance (Ohm)
Figure 7 - Loop Current (mA) Versus Loop Resistance (ohm) for Vbat = -48V
13
MT91610
Absolute Maximum Ratings*
Parameter 1 DC Supply Voltages Sym VDD VEE VBAT VRING VREF EE IRING TSTG PDISS -65 0 Min -0.3 +0.3 +0.3 Max +6.5 -6.5 -72 100 5 200 35 50 +150 0.10 500 Units V V V VRMS V V mA mA C W V
Preliminary Information
Comments
2 3 4 5 6 7 8 9
Ringing Voltage Voltage setting for Loop Current Overvoltage Tip/GND Ring/GND, Tip/Ring Ringing Current Tip / Ring Ground over-current Storage Temp Package Power Dissipation ESD maximum rating
Differentially across Tip & Ring Note 1 MAX 1ms (with power on)
Note 2
+85C max, VBAT = -48V
*Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Note 1: Refer to Figure 3 & 6 for appropriate biasing values Note 2: Tip and Ring drivers to be limited to about 50mA externally (Figure 5). If the UD pin is asserted for longer than 5 seconds, then PD should be asserted to power down the device. The device should then be checked (by de-asserting PD) every 5 seconds.
Recommended Operating Conditions
Parameter 1 Operating Supply Voltages Sym VDD VEE VBAT DCRI VRING FRING VREF 16 Min 4.75 -5.25 -72 5 Typ 5.00 -5.00 -48 60 20 1.67 80 Max 5.25 -4.75 -22 72 Units V V V V VRMS Hz V ILOOP = 25mA, VBAT = -48V Note 4 Test Conditions
50mA current capability Note 3
2 3 4
Ringing Voltage Ringing Frequency Voltage setting for Loop Current
5
Operating Temperature
TO
-40
+25
+85
C
Typical Figures are at 25C with nominal supply voltages and are for design aid only Note 3: For a 1.2Vrms 20Hz input at RV terminal (Figure 4) and with RC pin set to +5V. Note 4: Refer to Figure 3 & 6 for biasing values
14
Preliminary Information
DC Electrical Characteristics
Characteristics 1 Supply Current Sym IDD IEE IBAT IDD IEE IBAT ILOOP RLOOP Min Typ 8 6 28 300 300 1.8 25 1600 400 Max Units mA mA mA uA uA mA mA
PD= 0V
MT91610
Test Conditions VBAT= -48V lBAT ~ lLOOP + 3 mA PD = 5V VBAT = -48V VREF=1.67V ILOOP = 20mA VBAT = -48V ILOOP = 20mA VBAT = -22V
2
Supply Current
3 4
Constant Current Line Feed Operating Loop Constant Current Mode (including the DC resistance of the Telephone Set) Off Hook Detection Threshold RC, LR Input Low Voltage Input High Voltage PD, ESE Input Low Voltage Input High Voltage SHK Output Low Voltage Output High Voltage UnBalance Detection Threshold UD Output Low Voltage Output High Voltage Dial Pulse Distortion
5 6
SHK
12
mA
VIL VIH VIL VIH VOL VOH
IUD
0.5 4.5 0.5 4.5 0.5 4.5 12
V V V V V V mA
LIL = -1A LIH = 1A LIL= -1A LIH = 1A LOL = 7.5mA LOH = -1.5mA
7
8
9 10
VOL VOH
0.5 4.5 1 ms
LOL = 0.25mA LOH = -0.25mA
11
Electrical Characteristics are over Recommended Operating Conditions unless otherwise stated. Typical Figures are at 25C with nominal 5V and are for design aid only.
15
MT91610
AC Electrical Characteristics
Characteristics 1 3 4 5 6 7 8 9 10 11 Ring Trip Detect Time Return Loss (2W) Transhybrid Loss Output Impedance at VX Gain 4 to 2 Wire @ 1kHz Gain Relative to 1kHz Gain 2W to VX @ 1kHz Gain Relative to 1kHz Longitudinal to Metallic Balance at 2W Total Harmonic Distortion @2W @VX 12 13 Common Mode Rejection 2 Wire to Vx Idle Channel Noise @2W @VX 14 Power Supply Rejection Ratio at 2W and VX Vdd Vee 15 Line Reversal Recovery Timing TLRR PSR 23 23 30 50 CMR NC 12 12 45 LCL THD 0.3 0.3 50 1.0 1.0 46 -6.5 -1.5 Sym Tt RL THL 20 20 Min Typ 90 30 25 10 -1 0.15 -6 0.15 55 -5.5 -0.5 Max 200
Preliminary Information
Units mS
Test Conditions
dB
dB dB dB dB dB dB
300Hz to 3400Hz Note 5 300Hz to 3400Hz Note 5 AC small signal Note 5 300Hz to 3400Hz Note 5 300Hz to 3400Hz Input 2Vrms, 1KHz
% % dB
1Vrms, 1kHz @ 2W 1Vrms, 1KHz @ VR Input 2Vrms, 1KHz
dBrnC dBrnC
Cmessage Filter Fig. 4 Cmessage Filter Fig. 4
dB dB ms
0.1Vp-p @ 1kHz ILoop = 30 mA Note 6
Electrical Characteristics are over Recommended Operating Conditions unless otherwise stated. Typical Figures are at 25C with nominal 5V and are for design aid only. Note 5: Refer to Figure 4 & 5 for set up and component values. Note 6: TLRR is measured from the time when the LR pin is set to 0V (de-selected), to the time when the loop current is within 10% of its programmed steady state value.
16
Preliminary Information
Test Circuits
MT91610
Figures 8,9,10,11,12 are for illustrating the principles involved in making measurements and do not necessarily reflect the actual method used in production testing.
TIP Zo ILoop SLIC 6 R2 R1 C2 +5V
RING
Figure 8 - Loop Current Programming
27 TIP Zo __ 2 VS 25 R8
R9
VX
~
Zo __ 2
VTR
SLIC 24 R7 23
RING Gain = 20*Log(VX/VTR)
Figure 9 - 2-4 Wire Gain
25 TIP 24 28 Zo R10 R6 27 R9 VTR SLIC
VX
Gain = 20*Log(VTR/VS) THL = 20*Log(VX/VS)
RING
~V
S
Figure 10 - 4-2 Wire Gain & Transhybrid Loss
17
MT91610
Preliminary Information
TIP Zo __ 2 VTR VS SLIC
27
R9
25
VX
~
Zo __ 2 RING
Long. Bal. = 20*Log(VTR/VS) CMR = 20*Log(VX/VS)
Figure 11 - Longitudinal Balance & CMR
27 Zo R VS TIP
R9
23 VZ SLIC 22 R5 20 R4 RING
~
R
Gain = 20*Log(2*VZ/VS)
Figure 12 - Return Loss
18
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